Embedded multi-die interconnect bridge with improved power delivery

ABSTRACT

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include at least two integrated circuit dies that communicate using an embedded multi-die interconnect bridge (EMIB) in a substrate of the multi-chip package. The EMIB may receive power at contact pads formed at a back side of the EMIB that are coupled to a back side conductor on which the EMIB is mounted. The back side conductor may be separated into multiple regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal from a printed circuit board. These power supply voltage signals and data signals may be provided to the two integrated circuit dies through internal microvias or through-silicon vias formed in the EMIB.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/716,928, filed Apr. 8, 2022, which is a continuation of U.S. patentapplication Ser. No. 17/581,751, filed Jan. 21, 2022, which is acontinuation of U.S. patent application Ser. No. 15/439,118, filed onFeb. 22, 2017, the entire contents of which are hereby incorporated byreference herein.

BACKGROUND

This relates generally to integrated circuit packages, and moreparticularly, to integrated circuit packages with embedded multi-dieinterconnect bridges (EMIBs) that connect more than one integratedcircuit die.

An integrated circuit package typically includes an integrated circuitdie and a substrate on which the die is mounted. The die can be coupledto the substrate through bonding wires or solder bumps. Signals from theintegrated circuit die may then travel through the bonding wires orsolder bumps to the substrate.

As demands on integrated circuit technology continue to outstrip eventhe gains afforded by ever decreasing device dimensions, more and moreapplications demand a packaged solution with more integration thanpossible in one silicon die. In an effort to meet this need, more thanone die may be placed within a single integrated circuit package (i.e.,a multichip package). As different types of devices cater to differenttypes of applications, more dies may be required in some systems to meetthe requirements of high performance applications. Accordingly, toobtain better performance and higher density, an integrated circuitpackage may include multiple dies arranged laterally along the sameplane.

EMIBs are small silicon dies that are sometimes embedded in thesubstrate of a multichip package and are used to interconnect integratedcircuit dies within that multichip package. Traditionally, these EMIBShave limited power delivery capability compared to other interposertechnologies such as silicon interposers.

It is within this context that the embodiments described herein arise.

SUMMARY

An integrated circuit package may include a package substrate and one ormore integrated circuit dies mounted on the package substrate. Thepackage substrate may include an embedded multi-die interconnect bridge(EMIB) embedded within the package substrate. An EMIB is a silicon diethat may be used to interconnect two integrated circuits in a multi-chippackage. The integrated circuit dies mounted on the package substratemay communicate with one another through the EMIB. The EMIB may have afront side that faces the integrated circuit dies and a back side thatopposes the front side. The package substrate may include a conductivepath that is electrically coupled to the EMIB from the back side of theEMIB and that supplies power to the EMIB. The package substrate may bemounted on a printed circuit board that provides power to the EMIBthrough the conductive path.

The package substrate may also include a conductive layer (e.g., backside conductor) on which the EMIB is mounted. The conductive path may beconnected to the conductive layer and may provide power to the EMIBthrough the conductive layer. A patterned adhesive layer may be appliedto the conductive layer before the EMIB is mounted on the conductivelayer and may include openings that accommodate conductive pads (e.g.,contact pads) formed at the back side of the EMIB. In other words, oncethe EMIB is mounted on the conductive layer, the patterned adhesivelayer may laterally surround the conductive pads formed at the back sideof the EMIB. Additional contact pads may be formed at the front side ofthe EMIB.

The package substrate may include a first via directly connected to acontact pad formed at the front side of the EMIB, and may include asecond via that is coupled to a contact pad formed at the back side ofthe EMIB through the conductive layer. The second via may have adiameter that is greater than a diameter of the first via.

The EMIB may include a conductive routing trace (e.g., interconnect)that is coupled to the integrated circuit dies. A microvia formed in theEMIB may be coupled between one of the conductive pads formed at theback side of the EMIB and the conductive routing trace. Power supplyvoltage signals or data signals may be provided to the conductiverouting trace through the microvia.

The EMIB may include multiple through-silicon vias that extend from theback side of the EMIB to the front side of the EMIB. Thesethrough-silicon vias may be used to transfer power or data signals fromthe conductive path to the integrated circuit dies through the EMIB.

The conductive layer may include multiple conductive regions that areelectrically isolated from one another. Each region of the conductivelayer may receive a different power supply voltage signal or data signalfrom each other region of the conductive layer.

Fabricating an integrated circuit package may include multipleprocessing steps. A first dielectric layer may be formed. A via may beformed through the first dielectric layer. A conductive layer may beformed on the first dielectric layer in direct physical contact with thevia. Forming the conductive layer may involve forming multipleconductive regions that are electrically isolated from one another. Asilicon die (e.g., an EMIB) may be mounted on the conductive layer.Additional dielectric layers may be formed covering the silicon die. Afirst integrated circuit die may be mounted on the additional dielectriclayers. A second integrated circuit die may be mounted on the additionaldielectric layers. The silicon die may include a conductive routingtrace that couples the first integrated circuit die to the secondintegrated circuit die.

Before forming the additional dielectric layer, a second dielectriclayer may be formed on the first dielectric layer. A cavity may beformed in the second dielectric layer directly over the conductivelayer. Mounting the silicon die on the conductive layer may includeinserting the silicon die into the cavity. A patterned adhesive layermay be formed between the silicon die and the conductive layer. Thepatterned adhesive die may include a plurality of openings toaccommodate contact pads formed on a bottom surface of the silicone die.

Further features of the present invention, its nature and variousadvantages will be more apparent from the accompanying drawings and thefollowing detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an illustrative system of integrated circuitdevices operable to communicate with one another in accordance with anembodiment.

FIG. 2 is a diagram of an illustrative multichip package in accordancewith an embodiment.

FIG. 3 is a cross-sectional side view of an illustrative multichippackage that includes two die coupled together using an embeddedmulti-die interconnect bridge (EMIB) in accordance with an embodiment.

FIG. 4 is a top view of an illustrative multichip package that includestwo die coupled together using an EMIB in accordance with an embodiment.

FIG. 5 is a cross-sectional side view of an illustrative multichippackage that includes an EMIB having through-silicon vias in accordancewith an embodiment.

FIG. 6 is a cross-sectional side view of an illustrative EMIB havinginternal microvias in accordance with an embodiment.

FIG. 7A is a top view of an illustrative back side conductor for an EMIBthat is horizontally separated into three voltage regions that areelectrically isolated from one another in accordance with an embodiment.

FIG. 7B is a top view of an illustrative conductive back side conductorfor an EMIB that is vertically separated into three voltage regions inaccordance with an embodiment.

FIG. 7C is a top view of an illustrative conductive back side conductorthat is separated into three voltage regions and two signal regions,which are all electrically isolated from each other in accordance withan embodiment.

FIG. 8 is a flow chart showing illustrative steps for forming a packagesubstrate that includes an EMIB with improved power deliverycapabilities in accordance with an embodiment.

DETAILED DESCRIPTION

Embodiments of the present invention relate to integrated circuits, andmore particularly, to ways of improving power delivery through anembedded multi-die interconnect bridge in a multichip package.

As integrated circuit fabrication technology scales towards smallerprocess nodes, it becomes increasingly challenging to design an entiresystem on a single integrated circuit die (sometimes referred to as asystem-on-chip). Designing analog and digital circuitry to supportdesired performance levels while minimizing leakage and powerconsumption can be extremely time consuming and costly.

One alternative to single-die packages is an arrangement in whichmultiple dies are placed within a single package. Such types of packagesthat contain multiple interconnected dies may sometimes be referred toas systems-in-package (SiPs), multi-chip modules (MCM), or multichippackages. Placing multiple chips (dies) into a single package may alloweach die to be implemented using the most appropriate technology process(e.g., a memory chip may be implemented using the 28 nm technology node,whereas the radio-frequency analog chip may be implemented using the 45nm technology node), may increase the performance of die-to-dieinterface (e.g., driving signals from one die to another within a singlepackage is substantially easier than driving signals from one package toanother, thereby reducing power consumption of associated input-outputbuffers), may free up input-output pins (e.g., input-output pinsassociated with die-to-die connections are much smaller than pinsassociated with package-to-board connections), and may help simplifyprinted circuit board (PCB) design (i.e., the design of the PCB on whichthe multi-chip package is mounted during normal system operation).

In order to facilitate communications between two chips on a multi-chippackage, the package may include an embedded multi-die interconnectbridge (EMIB) that is designed and patented by INTEL Corporation. AnEMIB is a small silicon die that is embedded in the underlying substrateof a multi-chip package and that offers dedicated ultra-high-densityinterconnection between dies within the package. EMIBs generally includewires of minimal length, which help to significantly reduce loading anddirectly boost performance.

EMIB solutions may be advantageous over other multi-chip packagingschemes that use a silicon interposer, which is prone to issues such aswarpage and requires a comparatively large number of microbumps andthrough-silicon vias (TSVs) to be formed on and within the interposer,thereby reducing overall yield and increasing manufacturing complexityand cost. The number of dies that can be integrated using an interposeris also limited to that supported by EMIB technology.

The EMIB technology described above may be used as an interface betweenone or more integrated circuit dies in a system. FIG. 1 is a diagram ofan illustrative system 100 of interconnected electronic devices. Thesystem of interconnected electronic devices may have multiple electronicdevices such as device A, device B, device C, device D, andinterconnection resources 102. Interconnection resources 102 such asconductive lines and busses, optical interconnect infrastructure, orwired and wireless networks with optional intermediate switchingcircuitry may be used to send signals from one electronic device toanother electronic device or to broadcast information from oneelectronic device to multiple other electronic devices. For example, atransmitter in device B may transmit data signals to a receiver indevice C. Similarly, device C may use a transmitter to transmit data toa receiver in device B.

The electronic devices may be any suitable type of electronic devicethat communicates with other electronic devices. Examples of suchelectronic devices include basic electronic components and circuits suchas analog circuits, digital circuits, mixed-signal circuits, circuitsformed within a single package, circuits housed within differentpackages, circuits that are interconnected on a printed-circuit board(PCB), etc.

As shown in FIG. 2 , a multi-chip package 200 may include a main die202, a transceiver die 204, a memory die 206, and additional auxiliarydies 208. Main die 202, for example, may be a central processing unit(CPU), a graphics processing unit (GPU), an application-specificintegrated circuit (ASIC), a programmable logic device (PLD), or anyother desired processor or logic device. Secondary integrated circuitdies such as transceiver die 204, memory die 206, and auxiliary dies 208may be coupled to main die 202 and may communicate with main die 202.Memory die 206, for example, may be an erasable-programmable read-onlymemory (EPROM) chip, a non-volatile memory (e.g., 3D XPoint) chip, avolatile memory (e.g., high bandwidth memory) chip, or any othersuitable memory device. Auxiliary dies 208 may include additional memorydies, transceiver dies, programmable logic devices, and any othersuitable integrated circuit devices.

An EMIB may be embedded in a multi-chip package to connect two adjacentintegrated circuit dies on the package. As shown in FIG. 3 , main die202 and secondary die 205 may be mounted onto package substrate 300using solder bumps 304 and solder microbumps 305. Package substrate 300may be mounted onto printed circuit board (PCB) 350 using solder (e.g.,solder balls, solder bumps) 306. The terms solder “balls” or solder“bumps” may sometimes be use interchangeably. Signals (e.g., datasignals and power supply voltage signals) may be transferred between PCB350 and dies 202 and 205 through solder balls 306, package vias 308 inpackage 300, and solder bumps 304.

Main die 202 may be coupled to a secondary die 205 using EMIB 320 thatis embedded in package substrate 300. Signals being passed between maindie 202 and secondary die 205 may pass through interconnects (e.g.,conductive paths) 322 and microbumps 305. EMIB 320 may have a front sidethat faces main die 202 and secondary die 205 and may have a back sidethat faces package substrate 300. An EMIB is traditionally formed on asolid, electrically floating conductive plate for structural support. Itis therefore difficult to provide power to microbumps 305 that overlapwith regions 203 and 207 of main die 202 and secondary die 205, as powercannot be delivered vertically from the PCB through the EMIB to regions203 and 207 because back side routing is blocked by the conductiveplate.

FIG. 4 shows a top view of package substrate 300 in regions 203 and 207and illustrates possible means of power and ground signal delivery tomicrobump arrays in regions 203 and 207. Two microbump arrays in regions203 and 207 may overlap with EMIB 320 formed in package substrate 300.Each microbump array, for example, may correspond to an edge of anintegrated circuit die (e.g., main die 202 and secondary die 205 of FIG.3 ). Three different voltage signals may be applied to the pads ofpackage substrate 300: (1) a common voltage signal Vss (e.g., groundpower supply voltage signal), (2) a power supply voltage signal Vcc1 forregion 207 (e.g., for secondary die 205 in FIG. 3 ), and a power supplyvoltage signal Vcc2 for region 203 (e.g., for main die 202 of FIG. 3 ).It should be noted that a portion of the microbumps in region 203 mayalso receive power supply voltage signal Vcc1.

These power supply and common voltage signals may be delivered toperipheral microbumps in regions 203 and 207 without exceptional loss inpower efficiency. For example, voltage signals Vss, Vcc1, and Vcc2 maybe delivered to the microbumps at the edges of the microbump arrays ofregions 203 and 207 using conductors (e.g., copper traces) formed in atop layer of the package substrate.

Additionally, microbumps in the center (e.g., not at the periphery) ofthe microbump arrays of regions 203 and 207 may have voltage signalsVss, Vcc1, and Vcc2 routed to them by forming conductors (e.g., coppertraces) in a top layer of the package substrate arranged to extendvertically across a given microbump array. Only microbumps in the pathof one of these conductors may receive respective voltage signal carriedby that conductor. However, extending one of these conductors to coverthe entire width of a microbump array may undesirably result in a lossin power efficiency. It would therefore be advantageous to providealternate means of power delivery for microbumps in the center of themicrobump arrays of regions 203 and 207.

One alternative to the topside microbump power delivery described aboveis to deliver power and ground signals to the microbumps from the PCBvertically through the package substrate and the EMIB from the backside. As shown in FIG. 5 , main die 202 may be mounted onto packagesubstrate 300 using solder bumps (e.g., controlled collapse chipconnection (C4) bumps) 304 and microbumps 305. It should be noted thatthe pitch width of solder bumps 304 may be greater than the pitch widthof microbumps 305, such that microbumps 305 have greater connectiondensity than solder bumps 304. The diameter of microbumps 305 are alsogenerally smaller than the diameter of C4 bumps 304 (e.g., bumps 305 maybe at least two times smaller, at least four times smaller, etc.)

Solder bumps 304 may be provided with signals (e.g., data signals orpower supply voltage signals) from a printed circuit board (e.g., PCB350 of FIG. 3 ) through vias 504 and traces 502 formed in routing layers351-1, 351-2, 351-3, and 351-4 of package substrate 300. If desired, thepackage substrate may include additional layers (e.g., the number oflayers in the package substrate is not limited to four).

Microbumps 305 may be provided with signals (e.g., data signals or powersupply voltage signals) from EMIB 320 through vias 505 and traces 503.The signals provided to microbumps 305 may be received from another chipcoupled to EMIB 302 or from a PCB (e.g., PCB 350 of FIG. 3 ) on whichpackage substrate 300 is mounted. It should be noted that vias 505 maybe smaller than vias 504 and vias 504′.

EMIB 320 may be mounted on a back side conductor (e.g., conductive layeror copper conductive layer) 510 in layer 351-2 of package substrate 300using an adhesive layer 514 during fabrication of package substrate 300.A cavity 512 may be included adjacent to EMIB 320 in order to accountfor differences between the coefficient of thermal expansion betweenEMIB 320 and package substrate 300, which may reduce thermal stressesplaced on EMIB 320.

EMIB 320 may include through-silicon vias (TSVs) that extend verticallyfrom the front side of EMIB 320 to the back side of EMIB 320 to connectcontact pads 516 formed on the front side of EMIB 320 to contact pads518 formed on the back side of EMIB 320. Adhesive layer 514 may bepatterned to accommodate contact pads 518 to ensure that contact pads518 are in electrical contact with back side conductor 510. In otherwords, adhesive layer 514 may laterally surround contact pads 518 ofEMIB 320 without being interposed between contact pads 518 and back sideconductor 510.

In accordance with an embodiment, back side conductor 510 may receivepower supply voltage signals and/or data signals from a PCB (e.g., PCB350 of FIG. 3 ) through vias 504′ and traces 502′ and may provide thesesignals to contact pads 518 of EMIB 320. It should be noted that vias504′ may have a diameter that is larger than the diameter of vias 505.Having a larger diameter allows vias 504′ to carry more power than wouldbe achievable with vias having a comparatively smaller diameter.

By providing signals to EMIB 320 from the PCB through back sideconductor 510, vias 504′, and traces 502′, and providing power to one orboth circuit dies through TSVs 520 in EMIB 320, vertical powerdistribution may be achieved through EMIB 320.

Conventional EMIB arrangements lack such back side vertical powerdistribution paths and instead are limited to passing power betweenchips connected by the EMIB over the EMIB itself or by routing power tothese chips around the EMIB. Both of these conventional powerdistribution options disadvantageously reduce power efficiency of thesystem containing the EMIB by requiring smaller gauge traces or longertraces for power delivery compared to the vertical power distributionpath coupled to EMIB 320.

Thus, the vertical power distribution path coupled between the PCB andthe back side of EMIB 320 that includes back side conductor 510, vias504′, and traces 502′ is advantageous over these conventional EMIBarrangements in terms of power efficiency.

Signals may also be provided from the PCB to internal interconnects ofEMIB 320. As shown in FIG. 6 , EMIB 320 may include interconnects (e.g.,conductive routing traces) 602 and 604. Contact pads 518-1 and 518-2 mayreceive power supply voltage signals, ground voltage signals, or datasignals (e.g., from back side conductor 510 of FIG. 5 ), and may passthese signals to EMIB microvias 606 and 608. Microvia 606 may include aportion interposed between interconnect 602 and contact pad 518-1, suchthat signals received by contact pad 518-1 may be passed to interconnect602. Microvia 606 may also include a portion interposed betweeninterconnect 602 and contact pad 516-1, such that signals received bycontact pad 518-1 may also be passed to contact pad 516-1 and thereby toany microbumps coupled to contact pad 516-1.

Microvia 608 may only extend from contact pad 518-2 to interconnect 604.Contact pad 518-2 may pass received signals to interconnect 604 throughmicrovia 608. Optionally, an additional microvia 608′ may be interposedbetween interconnect 602 and interconnect 604 and/or may be interposedbetween contact pad 516-2 and interconnect 602. This arrangement allowsfor signals received by contact pad 518-2 to be passed to each ofinterconnects 602 and 604 and to contact pad 516-2 and thereby to anymicrobumps coupled to contact pad 516-2.

If desired, back side conductor 510 of FIG. 5 may be separated intomultiple regions that are electrically isolated from one another, whereeach region may receive a different power supply voltage signal, groundvoltage signal, or data signal from the PCB. Some possible arrangementsof back side conductor 510 are described below in connection with FIGS.7A-7C.

As shown in FIG. 7A, back side conductor 510 may be horizontallyseparated into regions 700, 702, and 704 that are each electricallyisolated from one another. Power supply voltage signal Vcc1 may beapplied to region 702. Common (e.g., ground) power supply voltage signalVss may be applied to region 700. Power supply voltage signal Vcc2 maybe applied to region 704. This arrangement of back side conductor 510allows for the three different types of power/ground voltage signals tobe applied to the microbumps of either of the two chips connected to oneanother through the EMIB (e.g., EMIB 320) attached to back sideconductor 510.

As shown in FIG. 7B, back side conductor 510 may be vertically separatedinto regions 710, 712, and 714 that are each electrically isolated fromone another. Power supply voltage signal Vcc2 may be applied to region712. Common (e.g., ground) power supply voltage signal Vss may beapplied to region 710. Power supply voltage signal Vcc3 may be appliedto region 714. This arrangement of back side conductor 510 allows forpower supply voltage signal Vcc2 to be applied to the microbumps of oneof the two chips connected to one another through the EMIB (e.g., EMIB320) attached to back side conductor 510, for power supply voltagesignal Vcc3 to be applied to the microbumps of the other chip of the twochips, and for common signal Vss to be applied to either or both of thetwo chips.

As shown in FIG. 7C, back side conductor 510 may be separated into threevertically separated regions that are each electrically isolated fromone another, similar to the arrangement of FIG. 7B. Each verticallyseparated region may receive one of power supply voltage signal Vcc1,power supply voltage signal Vcc2, and common signal Vss. Back sideconductor 510 may further include two horizontal regions 750 and 752that are electrically isolated from one another and from the threeseparated vertical regions. Data signal SIG1 may be applied to region750 and data signal SIG2 may be applied to region 752. In this way, datasignals may also be passed to the EMIB (e.g., EMIB 320) that is mountedon back side conductor 510.

The arrangements of back side conductor 510 shown in FIGS. 7A-C aremerely illustrative. If desired, back side conductor 510 may include anynumber of regions that are electrically isolated from one another andthat each receive a different power supply voltage signal or data signal(e.g., from a printed circuit board).

FIG. 8 shows the illustrative steps performed when manufacturing packagesubstrate 300 of FIG. 5 .

At step 800, first dielectric layer 351-1 may be formed. Vias 504 and504′ in layer 351-1 and traces 502 and 502′ may also be formed at thisstep.

At step 802, second dielectric layer 351-2 may be formed. Via 504, trace502, and back side conductor 510 may also be formed in layer 351-2 atthis step. As described in connection with FIGS. 7A-7C above, back sideconductor 510 may be formed having multiple regions that areelectrically isolated from one another and that each receive a differentpower supply voltage signal or data signal.

At step 804, third dielectric layer 351-3 may be formed. Via 504 andtrace 502 may be formed in layer 351-3 at this step.

At step 806, a cavity may be formed in second dielectric layer 351-2 andthird dielectric layer 351-3 (e.g., using photolithographic etching,lapping, or drilling). The cavity may overlap back side conductor 510and may extend through layers 351-2 and 351-3 so as to expose back sideconductor 510.

At step 808, adhesive layer 514 may be patterned within the cavity, suchthat openings are formed in adhesive layer 514 to accommodate contactpads 518 of EMIB 320.

At step 810, EMIB 320 may be placed on the patterned adhesive within thecavity, and may thereby be mounted on back side conductor 510. It shouldbe noted that any TSVs or internal EMIB microvias may already be formedwithin EMIB 320 prior to the placement of EMIB 320 in the cavity (e.g.,during fabrication of EMIB 320).

At step 812, remaining dielectric layers including dielectric layer851-4 and the portion of dielectric layer 851-3 disposed over EMIB 320may be formed. Vias 504 and 505 and traces (e.g., via pads) 502 and 503may also be formed at this step.

Optionally, step 804 may be omitted and the entirety of layer 851-3 maybe formed during step 812. In this optional case, the cavity only needsto be formed in second dielectric layer 851-2 during step 806.

The embodiments thus far have been described with respect to integratedcircuits. The methods and apparatuses described herein may beincorporated into any suitable circuit. For example, they may beincorporated into numerous types of devices such as programmable logicdevices, application specific standard products (ASSPs), and applicationspecific integrated circuits (ASICs). Examples of programmable logicdevices include programmable arrays logic (PALs), programmable logicarrays (PLAs), field programmable logic arrays (FPLAs), electricallyprogrammable logic devices (EPLDs), electrically erasable programmablelogic devices (EEPLDs), logic cell arrays (LCAs), complex programmablelogic devices (CPLDs), and field programmable gate arrays (FPGAs), justto name a few.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the art. Theforegoing embodiments may be implemented individually or in anycombination.

What is claimed is:
 1. A multi-chip package, comprising: an interconnectbridge having a first contact pad and a second contact pad thereon, theinterconnect bridge comprising a silicon die, wherein the interconnectbridge is over a conductor; an adhesive layer vertically between theinterconnect bridge and the conductor, the adhesive layer in contactwith the silicon die of the interconnect bridge; a first dielectriclayer, the first dielectric layer laterally adjacent the interconnectbridge, and the first dielectric layer laterally adjacent the adhesivelayer; a second dielectric layer on the first dielectric layer and onthe interconnect bridge, the second dielectric layer over the conductor;a first via in the second dielectric layer, the first via coupled to thefirst contact pad; a second via in the second dielectric layer, thesecond via coupled to the second contact pad; a third via in the seconddielectric layer, the third via coupled to a fourth via in the firstdielectric layer; a third dielectric layer on the second dielectriclayer, the third dielectric layer over the interconnect bridge and overthe conductor; a first conductive trace in the third dielectric layer,the first conductive trace coupled to the first via; a second conductivetrace in the third dielectric layer, the second conductive trace coupledto the second via; a third conductive trace in the third dielectriclayer, the third conductive trace coupled to the third via; a fifth viain the third dielectric layer, the fifth via coupled to the firstconductive trace; a sixth via in the third dielectric layer, the sixthvia coupled to the second conductive trace; a seventh via in the thirddielectric layer, the seventh via coupled to the third conductive trace;a first die over the third dielectric layer, the first die over theinterconnect bridge and over the conductor, and the first die coupled tothe fifth via and to the sixth via and to the seventh via; and a seconddie over and coupled to the interconnect bridge.
 2. The multi-chippackage of claim 1, wherein the second die is coupled to the first dieby the interconnect bridge.
 3. The multi-chip package of claim 1,wherein the first dielectric layer is in contact with the conductor. 4.The multi-chip package of claim 1, wherein the interconnect bridge islaterally spaced apart from the first dielectric layer.
 5. Themulti-chip package of claim 1, further comprising: a fourth dielectriclayer below the first dielectric layer.
 6. The multi-chip package ofclaim 1, wherein the conductor comprises multiple regions that areelectrically isolated from one another.
 7. The multi-chip package ofclaim 1, wherein the conductor is to receive a power supply voltagesignal.
 8. The multi-chip package of claim 1, wherein the conductor isto receive a data signal.
 9. The multi-chip package of claim 1, furthercomprising: one or more through silicon vias in the silicon die of theinterconnect bridge.
 10. The multi-chip package of claim 1, furthercomprising: a cavity laterally between the interconnect bridge and thefirst dielectric layer.
 11. The multi-chip package of claim 1, whereinthe first die is a main die, and the second die is a secondary die. 12.The multi-chip package of claim 11, wherein the main die is a dieselected from the group consisting of a central processing unit (CPU)die, a graphics processing unit (GPU) die, and an application-specificintegrated circuit (ASIC) die, and wherein the secondary die is a dieselected from the group consisting of a memory die and a transceiverdie.
 13. A multi-chip package, comprising: a silicon die having a firstcontact pad and a second contact pad thereon, the silicon die over abackside conductor; a non-conductive intervening layer verticallybetween the silicon die and the backside conductor, the non-conductiveintervening layer in contact with the silicon die; a first dielectriclaterally adjacent the silicon die and laterally adjacent thenon-conductive intervening layer; a second dielectric on the firstdielectric and on the silicon die, the second dielectric over thebackside conductor; a first conductive via, a second conductive via, anda third conductive via in the second dielectric, the first conductivevia coupled to the first contact pad, the second conductive via coupledto the second contact pad, and the third conductive via coupled to afourth conductive via in the first dielectric; a third dielectric on thesecond dielectric, the third dielectric over the silicon die and overthe backside conductor; a first conductor and a second conductor in thethird dielectric, the first conductor coupled to the first conductivevia, and the second conductor coupled to the second conductive via; athird conductor in the third dielectric, the third conductor coupled tothe third conductive via; a fifth conductive via, a sixth conductivevia, and a seventh conductive via in the third dielectric, the fifthconductive via coupled to the first conductor, the sixth conductive viacoupled to the second conductor, and the seventh conductive via coupledto the third conductor; a main die over the third dielectric, the maindie over the silicon die and over the conductor, and the main diecoupled to the fifth conductive via and to the sixth conductive via andto the seventh conductive via; and a second die over and coupled to thesilicon die.
 14. The multi-chip package of claim 13, wherein the seconddie is coupled to the main die by the silicon die.
 15. The multi-chippackage of claim 13, wherein the first dielectric is in contact with thebackside conductor, and wherein the silicon die is laterally spacedapart from the first dielectric.
 16. The multi-chip package of claim 13,further comprising: a fourth dielectric below the first dielectric. 17.The multi-chip package of claim 13, wherein the backside conductorcomprises multiple regions that are electrically isolated from oneanother.
 18. A system, comprising: a printed circuit board; a packagesubstrate coupled to the printed circuit board, the package substratecomprising: a backside conductor; an embedded multi-die interconnectbridge over the backside conductor, the embedded multi-die interconnectbridge having a first contact pad and a second contact pad thereon; anadhesive layer vertically between the embedded multi-die interconnectbridge and the backside conductor, the adhesive layer in contact withthe embedded multi-die interconnect bridge; a first via, a second viaand a third via in a first level above the embedded multi-dieinterconnect bridge, the first via coupled to the first contact pad, thesecond via coupled to the second contact pad, and the third via coupledto a fourth via below the first level; a first conductive trace, asecond conductive trace and a third conductive trace in a second level,the second level above the first level, the first conductive tracecoupled to the first via, the second conductive trace coupled to thesecond via, and the third conductive trace coupled to the third via; anda fifth via, a sixth via and a seventh via in a third level, the thirdlevel above the second level, the fifth via coupled to the firstconductive trace, the sixth via coupled to the second conductive trace,and the seventh via coupled to the third conductive trace; a first dieover the package substrate, the first die over the embedded multi-dieinterconnect bridge and over the backside conductor, and the first diecoupled to the fifth via and to the sixth via and to the seventh via;and a second die over the package substrate and coupled to the embeddedmulti-die interconnect bridge.
 19. The system of claim 18, wherein thesecond die is coupled to the first die by the embedded multi-dieinterconnect bridge.
 20. The system of claim 18, wherein the backsideconductor comprises multiple regions that are electrically isolated fromone another.